Invention Grant
US09306032B2 Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
有权
在替代栅极工艺中使用锥形层间电介质形成自对准金属栅极结构的方法
- Patent Title: Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
- Patent Title (中): 在替代栅极工艺中使用锥形层间电介质形成自对准金属栅极结构的方法
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Application No.: US14062909Application Date: 2013-10-25
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Publication No.: US09306032B2Publication Date: 2016-04-05
- Inventor: Ching-Ling Lin , Chih-Sen Huang , Po-Chao Tsao , Ching-Wen Hung , Jia-Rong Wu , Chien-Ting Lin
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L29/66
Abstract:
A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.
Public/Granted literature
- US20150118835A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2015-04-30
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