公开(公告)号：US09530862B2

公开(公告)日：2016-12-27

申请号：US14811814

申请日：2015-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L21/4763 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

公开(公告)号：US09337260B2

公开(公告)日：2016-05-10

申请号：US14549559

申请日：2014-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract translation: 半导体结构包括在基板中的多个第一绝缘体，围绕所述基板中的所述第一绝缘体的侧壁和底部的公共绝缘层，以及在所述公共绝缘层上的所述基板的悬置部分。

公开(公告)号：US09330980B2

公开(公告)日：2016-05-03

申请号：US14659576

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/76 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L21/823468 ,  H01L21/02068 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括第一栅极和第二栅极，第一间隔物和第二间隔物，两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中，其中第一间隔物和第二间隔物具有不同的厚度，并且第一外延结构之间的间隔不同于 第二外延结构。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09306032B2

公开(公告)日：2016-04-05

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US09208276B1

公开(公告)日：2015-12-08

申请号：US14822907

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

公开(公告)号：US09190291B2

公开(公告)日：2015-11-17

申请号：US13934236

申请日：2013-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao ,  Jun-Jie Wang ,  Chih-Sen Huang

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/3086 ,  H01L29/66795

Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.

Abstract translation: 鳍状结构形成工序包括以下工序。 第一心轴和第二心轴形成在基底上。 形成第一间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻暴露的第一间隔物材料以在第一心轴旁边的基底上形成第一间隔物。 形成第二间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻第二间隔物材料和第一间隔物材料以在第二心轴旁边的基底上形成第二间隔物，以及在第一心轴旁边的包括在基底上的第一间隔物的第三间隔物。 第二间隔物和第三间隔物的布局被转移到基底，因此分别形成具有不同宽度的第二鳍状结构和第一鳍状结构。

公开(公告)号：US09159798B2

公开(公告)日：2015-10-13

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US09117925B2

公开(公告)日：2015-08-25

申请号：US13756464

申请日：2013-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.

Abstract translation: 外延工艺包括以下步骤。 提供了包括第一区域和第二区域的基板。 第一栅极和第二栅极分别形成在第一区域和第二区域的基板上。 第一间隔物和第二间隔物同时分别形成在第一栅极和第二栅极旁边的基板上。 在第一间隔物旁边形成第一外延结构，然后通过第一间隔物和第二间隔物分别在第二间隔物旁边形成第二外延结构。

公开(公告)号：US20150221645A1

公开(公告)日：2015-08-06

申请号：US14681081

申请日：2015-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0611 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7851

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract translation: 半导体集成电路包括衬底，形成在衬底上的多栅极晶体管器件和形成在衬底中的n阱电阻器。 衬底包括多个第一隔离结构和至少形成在其中的第二隔离结构。 第一隔离结构的深度小于第二隔离结构的深度。 多栅晶体管器件包括多个翅片结构，并且翅片结构彼此平行并且通过第一隔离结构彼此间隔开。 n阱电阻器包括至少一个第一隔离结构。 n阱电阻器和多栅极晶体管器件通过第二隔离结构彼此电隔离。

公开(公告)号：US20150179457A1

公开(公告)日：2015-06-25

申请号：US14639134

申请日：2015-03-05

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，使得栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，并且图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后在栅电极的每个侧壁上形成间隔物。 随后，形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。