公开(公告)号：US12068309B2

公开(公告)日：2024-08-20

申请号：US17585582

申请日：2022-01-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20230197718A1

公开(公告)日：2023-06-22

申请号：US17668393

申请日：2022-02-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin

IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L27/0296 ,  H01L29/42356 ,  H01L29/42364 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823462 ,  H01L21/823475

摘要： A semiconductor device includes a substrate, a first transistor, a second transistor and a third transistor. The substrate includes a high-voltage (HV) area, a medium-voltage (MV) area, and a low-voltage (LV) area. The first transistor is disposed in the HV area and includes a first gate dielectric layer and a first gate electrode. The second transistor is disposed in the LV area and includes a plurality of fin-shaped structures and a second gate electrode. The third transistor is disposed in the MV area and includes a third gate dielectric layer and a third gate electrode. The topmost surfaces of the first gate electrode, the second gate electrode and the third gate electrode are coplanar with each other.

公开(公告)号：US20230154514A1

公开(公告)日：2023-05-18

申请号：US17548583

申请日：2021-12-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC分类号： G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

CPC分类号： G11C11/161 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  H01L27/222

摘要： The invention provides a semiconductor structure, which comprises an MTJ (magnetic tunneling junction) stacked structure arranged on a substrate, and a SOT (spin orbit torque) layer arranged on the MTJ stacked structure, wherein the SOT layer comprises a first part with a thick thickness and two second parts with a thin thickness.

公开(公告)号：US11387408B2

公开(公告)日：2022-07-12

申请号：US17131767

申请日：2020-12-23

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC分类号： H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

摘要： A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US10727397B1

公开(公告)日：2020-07-28

申请号：US16261524

申请日：2019-01-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L27/108 ,  H01L43/10

摘要： A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US20180288326A1

公开(公告)日：2018-10-04

申请号：US16001367

申请日：2018-06-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ting Lin

IPC分类号： H04N5/232 ,  G02B26/10 ,  H04N5/225 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L21/764 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/02

CPC分类号： H04N5/23238 ,  G02B26/101 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/32135 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H04N5/2254 ,  H04N5/2259 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23287

摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

公开(公告)号：US09847403B2

公开(公告)日：2017-12-19

申请号：US14855357

申请日：2015-09-15

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ting Lin ,  Shih-Fang Tzou

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535

CPC分类号： H01L29/6656 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes. Each of the spacers has an inner sidewall and an outer sidewall. The contact structure is disposed between the gate electrodes, and its bottom is in direct contact with all the region of the outer sidewall of the spacers.

公开(公告)号：US20170194423A1

公开(公告)日：2017-07-06

申请号：US15011996

申请日：2016-02-01

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ting Lin

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/283 ,  H01L21/764 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/66

CPC分类号： H04N5/23238 ,  G02B26/101 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/32135 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H04N5/2254 ,  H04N5/2259 ,  H04N5/23254 ,  H04N5/23258 ,  H04N5/23287

摘要： A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a gate structure, a first dielectric layer and two air gaps. The gate structure is disposed on the substrate. The gate structure has two opposite side walls. The gate structure comprises a U-shaped structure and a metal gate electrode. The U-shaped structure defines an opening toward upside, and comprises a work function layer. The metal gate electrode is disposed in the opening defined by the U-shaped structure. A level of a top surface of the U-shaped structure is lower than a level of a top surface of the metal gate electrode. The first dielectric layer is disposed on the substrate adjacent to the gate structure. Each of the two air gaps is formed between the first dielectric layer and one of the two opposite side walls of the gate structure.

公开(公告)号：US20170125579A1

公开(公告)日：2017-05-04

申请号：US15399755

申请日：2017-01-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ting Lin

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/785 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/32131 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

摘要： A semiconductor device includes: a substrate having a first fin-shaped structure and a second fin-shaped structure thereon, a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure, a gate isolation directly on the second fin-shaped structure, and a gate line on the STI and the first fin-shaped structure. Preferably, the gate line includes a L-shaped structure.

公开(公告)号：US09601600B2

公开(公告)日：2017-03-21

申请号：US14855793

申请日：2015-09-16

申请人： United Microelectronics Corp.

发明人： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Cho-Han Fan ,  Chien-Ting Lin

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66795 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

摘要： A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.