Invention Grant
US09318404B2 Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
有权
半导体器件和形成应力消除通孔的方法,用于改进扇出WLCSP封装
- Patent Title: Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
- Patent Title (中): 半导体器件和形成应力消除通孔的方法,用于改进扇出WLCSP封装
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Application No.: US13759911Application Date: 2013-02-05
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Publication No.: US09318404B2Publication Date: 2016-04-19
- Inventor: Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L23/00 ; H01L23/538 ; H01L23/36 ; H01L23/498

Abstract:
A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.
Public/Granted literature
- US20140217597A1 Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package Public/Granted day:2014-08-07
Information query
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