公开(公告)号：US08912650B2

公开(公告)日：2014-12-16

申请号：US13846742

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

Abstract translation: 半导体器件具有形成在半导体管芯上的第一导电层的半导体管芯。 第一绝缘层形成在半导体管芯上，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 互连结构形成在第二绝缘层的开口内的第一和第二导电层之上。 去除第二绝缘层。 互连结构可以是导电柱或导电垫。 凸起材料可以形成在导电柱上。 在导电柱或垫上方形成一层厚度小于1微米的保护涂层以减少氧化。 通过将导电柱或垫浸入含有锡或铟的浴中形成保护涂层。

公开(公告)号：US20130228919A1

公开(公告)日：2013-09-05

申请号：US13846742

申请日：2013-03-18

Applicant: STATS CHIPPAC, LTD.

Inventor： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC: H01L23/00

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

Abstract translation: 半导体器件具有形成在半导体管芯上的第一导电层的半导体管芯。 第一绝缘层形成在半导体管芯上，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 互连结构形成在第二绝缘层的开口内的第一和第二导电层之上。 去除第二绝缘层。 互连结构可以是导电柱或导电垫。 凸起材料可以形成在导电柱上。 在导电柱或垫上方形成一层厚度小于1微米的保护涂层以减少氧化。 通过将导电柱或垫浸入含有锡或铟的浴中形成保护涂层。

公开(公告)号：US09318404B2

公开(公告)日：2016-04-19

申请号：US13759911

申请日：2013-02-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.

Abstract translation: 半导体器件包括半导体管芯。 密封剂设置在半导体管芯周围以形成周边区域。 在半导体管芯和密封剂的第一表面上形成互连结构。 多个通孔部分地通过密封剂的周边区域形成并偏离半导体管芯。 密封剂的一部分设置在与第一表面相对的半导体管芯的第二表面上。 多个通孔包括大于该密封剂部分的厚度的深度。 多个通路的第一部分形成为从半导体管芯的一侧偏移的行。 多个通孔的第二部分形成为从半导体管芯的拐角偏移的通孔阵列。 设置在多个通孔内的修补材料。

公开(公告)号：US20130277851A1

公开(公告)日：2013-10-24

申请号：US13917982

申请日：2013-06-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Pandi Chelvam Marimuthu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract translation: 半导体器件具有布置在半导体管芯的周边区域中的模块化互连单元或互连结构。 密封剂沉积在半导体管芯和互连结构上。 在半导体管芯和互连结构之上形成第一绝缘层。 在互连结构上的第一绝缘层中形成多个开口。 开口的间距为40微米。 开口包括圆形，环形，十字形或格子形状。 导电层沉积在第一绝缘层上。 导电层包括平坦表面。 在导电层上形成第二绝缘层。 去除一部分密封剂以露出半导体管芯和互连结构。 模块化互连单元包括垂直互连结构。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。

公开(公告)号：US20140217597A1

公开(公告)日：2014-08-07

申请号：US13759911

申请日：2013-02-05

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.

Abstract translation: 半导体器件包括半导体管芯。 密封剂设置在半导体管芯周围以形成周边区域。 在半导体管芯和密封剂的第一表面上形成互连结构。 多个通孔部分地通过密封剂的周边区域形成并偏离半导体管芯。 密封剂的一部分设置在与第一表面相对的半导体管芯的第二表面上。 多个通孔包括大于该密封剂部分的厚度的深度。 多个通路的第一部分形成为从半导体管芯的一侧偏移的行。 多个通孔的第二部分形成为从半导体管芯的拐角偏移的通孔阵列。 设置在多个通孔内的修补材料。

公开(公告)号：US09837303B2

公开(公告)日：2017-12-05

申请号：US13917982

申请日：2013-06-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Pandi Chelvam Marimuthu

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/76802 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.