发明授权
US09330743B2 Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same
有权
电阻型存储器件的存储器核心，电阻型存储器件以及感测数据的方法
- 专利标题： Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same
- 专利标题（中）： 电阻型存储器件的存储器核心，电阻型存储器件以及感测数据的方法
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申请号： US14677991申请日： 2015-04-03
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公开(公告)号： US09330743B2公开(公告)日： 2016-05-03
- 发明人: Chan-Kyung Kim , Kee-Won Kwon , Su-A Kim , Chul-Woo Park , Jae-Youn Youn
- 申请人： Chan-Kyung Kim , Kee-Won Kwon , Su-A Kim , Chul-Woo Park , Jae-Youn Youn
- 申请人地址： KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- 专利权人： SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人： SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址： KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- 代理机构： Muir Patent Law, PLLC
- 优先权： KR10-2014-0072635 20140616
- 主分类号： G11C11/00
- IPC分类号： G11C11/00 ; G11C11/16 ; G11C5/08 ; G11C7/06 ; G11C5/02 ; G11C13/00 ; G11C11/4091
摘要：
A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.