公开(公告)号：US20170221538A1

公开(公告)日：2017-08-03

申请号：US15388419

申请日：2016-12-22

申请人： CHAN KYUNG KIM

发明人： CHAN KYUNG KIM

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1697

摘要： A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

公开(公告)号：US20130322162A1

公开(公告)日：2013-12-05

申请号：US13907223

申请日：2013-05-31

申请人： YUN-SANG LEE ,  DONG-SEOK KANG ,  SANG-BEOM KANG ,  CHAN-KYUNG KIM ,  CHUL-WOO PARK ,  DONG-HYUN SOHN ,  HYUNG-ROK OH

发明人： YUN-SANG LEE ,  DONG-SEOK KANG ,  SANG-BEOM KANG ,  CHAN-KYUNG KIM ,  CHUL-WOO PARK ,  DONG-HYUN SOHN ,  HYUNG-ROK OH

IPC分类号： G11C11/16 ,  G11C7/12

CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE)

摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）

公开(公告)号：US20130148429A1

公开(公告)日：2013-06-13

申请号：US13705143

申请日：2012-12-04

申请人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C7/06 ,  G11C11/16 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

摘要翻译： 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。

公开(公告)号：US20120075024A1

公开(公告)日：2012-03-29

申请号：US13308923

申请日：2011-12-01

申请人： Chan-Kyung KIM

发明人： Chan-Kyung KIM

IPC分类号： H03K3/03

CPC分类号： H03K3/354 ,  G11C7/22 ,  G11C7/222

摘要： One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.

摘要翻译： 振荡器的一个实施例包括第一饥饿逆变器和第二饥饿逆变器。 第二饥饿逆变器的内逆变器与第一饥饿逆变器的内逆变器交叉耦合。 振荡器还包括连接到第一饥饿逆变器的内逆变器的输出的第一反相器和连接到第二饥饿逆变器的内逆变器的输出的第二反相器。

公开(公告)号：US08089320B2

公开(公告)日：2012-01-03

申请号：US12684332

申请日：2010-01-08

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： H03B27/00

CPC分类号： H03L7/099 ,  H03K3/0231 ,  H03L2207/06

摘要： In one embodiment, the differential amplifier (DA) includes a first inverter inverting a first input signal and outputting the inverted first input signal to a current supply controller and a current drain controller. A second inverter inverts the first input signal and outputs the inverted first input signal as an output signal of the DA. The current supply controller supplies current to the first and second inverters in response to the inverted first input signal output from the first inverter during a first period. The current drain controller drains current from the first and second inverters in response to the inverted first input signal output from the first inverter during a second period. The output signal of the DA and the first input signal have differential phases with respect to each other and oscillate between logic high and low levels during the first period and the second period.

摘要翻译： 在一个实施例中，差分放大器（DA）包括反相第一输入信号并将反相的第一输入信号输出到电流供应控制器和电流消耗控制器的第一反相器。 第二个反相器将第一输入信号反相并输出反相的第一输入信号作为DA的输出信号。 电流供应控制器响应于在第一时段期间从第一逆变器输出的反相的第一输入信号，向第一和第二逆变器提供电流。 电流漏极控制器响应于在第二周期期间从第一反相器输出的反相的第一输入信号，从第一和第二反相器引出电流。 DA和第一输入信号的输出信号在第一周期和第二周期期间彼此具有差分相位并且在逻辑高电平和低电平之间振荡。

公开(公告)号：US07944244B2

公开(公告)日：2011-05-17

申请号：US12894631

申请日：2010-09-30

申请人： Sang-soon Lim ,  Chan-kyung Kim

发明人： Sang-soon Lim ,  Chan-kyung Kim

IPC分类号： H03K19/20

CPC分类号： H03K19/1736

摘要： Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group.

摘要翻译： 提供了能够通过使用单个逻辑门电路来执行多个逻辑运算的逻辑门装置。 多功能逻辑门装置包括上拉开关单元，其具有分别连接到多个输入端的第一组的输入开关和连接到选择端或逻辑反相选择端的第一组的选择开关，所述拉 所述开关单元根据所述选择端子和所述反相选择端子的逻辑电平将所述第一组的输入开关串联或并联连接在电源和输出端子之间。 多功能逻辑门包括下拉开关单元，其具有分别连接到多个输入端子的第二组的输入开关和连接到选择端子或反相选择端子的第二组的选择开关，下拉开关单元 开关单元根据选择端子和反相选择端子的逻辑电平将第二组的输入开关并联或串联连接在输出端子与接地端子之间。 第二组的输入开关的连接与第一组的输入开关的连接互补地相反。

公开(公告)号：US07830179B2

公开(公告)日：2010-11-09

申请号：US12276819

申请日：2008-11-24

申请人： Sang-soon Lim ,  Chan-kyung Kim

发明人： Sang-soon Lim ,  Chan-kyung Kim

IPC分类号： H03K19/20

CPC分类号： H03K19/1736

摘要： Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group.

摘要翻译： 提供了能够通过使用单个逻辑门电路来执行多个逻辑运算的逻辑门装置。 多功能逻辑门装置包括上拉开关单元，其具有分别连接到多个输入端的第一组的输入开关和连接到选择端或逻辑反相选择端的第一组的选择开关，所述拉 所述开关单元根据所述选择端子和所述反相选择端子的逻辑电平将所述第一组的输入开关串联或并联连接在电源和输出端子之间。 多功能逻辑门包括下拉开关单元，其具有分别连接到多个输入端子的第二组的输入开关和连接到选择端子或反相选择端子的第二组的选择开关，下拉开关单元 开关单元根据选择端子和反相选择端子的逻辑电平将第二组的输入开关并联或串联连接在输出端子与接地端子之间。 第二组的输入开关的连接与第一组的输入开关的连接互补地相反。

公开(公告)号：US07683726B2

公开(公告)日：2010-03-23

申请号：US12078851

申请日：2008-04-07

申请人： Chan Kyung Kim

发明人： Chan Kyung Kim

IPC分类号： H03B27/00

CPC分类号： H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03K2005/00286 ,  H03L7/0995

摘要： A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.

摘要翻译： 提供压控振荡器（VCO）。 VCO可以包括可以具有多个延迟单元并且可以输出第一差分振荡信号的第一环形振荡电路，以及可以具有多个延迟单元并且可以输出第二差分振荡信号的第二环形振荡电路。 第一环形振荡电路的延迟单元可以分别交叉耦合到第二环形振荡电路的对应的延迟单元。 每个延迟单元可以包括差分放大电路，其可以基于第一控制信号输出第一差分信号，并且可以并联连接到差分放大电路的一对输出端子的负电阻电路可以接收 第二差分信号可以基于第二控制信号调整第一差分信号的相位，然后可以输出第一差分信号。

公开(公告)号：US10090035B2

公开(公告)日：2018-10-02

申请号：US15388419

申请日：2016-12-22

申请人： Chan Kyung Kim

发明人： Chan Kyung Kim

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/16

摘要： A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

公开(公告)号：US09183910B2

公开(公告)日：2015-11-10

申请号：US13907223

申请日：2013-05-31

申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

IPC分类号： G11C11/16 ,  G11C7/12

CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。