Invention Grant
US09331672B2 Driver circuit with gate clamp supporting stress testing 有权
驱动电路与门夹支持压力测试

Driver circuit with gate clamp supporting stress testing
Abstract:
A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.
Public/Granted literature
Information query
Patent Agency Ranking
0/0