Invention Grant
- Patent Title: Metal stack for reduced gate resistance
- Patent Title (中): 用于降低栅极电阻的金属叠层
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Application No.: US14583835Application Date: 2014-12-29
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Publication No.: US09343372B1Publication Date: 2016-05-17
- Inventor: Ruqiang Bao , Unoh Kwon , Rekha Rajaram , Keith Kwong Hon Wong
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries, Inc.
- Current Assignee: GlobalFoundries, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/40 ; H01L29/51 ; H01L21/3213 ; H01L29/66 ; H01L29/49
Abstract:
A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.
Information query
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