公开(公告)号：US10361132B2

公开(公告)日：2019-07-23

申请号：US15476158

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Takashi Ando ,  Aritra Dasgupta ,  Kai Zhao ,  Unoh Kwon ,  Siddarth A. Krishnan

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/285 ,  H01L21/311 ,  H01L27/092 ,  H01L21/8238

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

公开(公告)号：US10109722B2

公开(公告)日：2018-10-23

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/3105

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

公开(公告)号：US09343372B1

公开(公告)日：2016-05-17

申请号：US14583835

申请日：2014-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Rekha Rajaram ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

Abstract: A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.

Abstract translation: 一种方法包括在衬底上形成n-FET器件和p-FET器件，n-FET器件和p-FET器件中的每一个包括由上述钛 - 碳化铝（TiAlC）层和 与氮化钛（TiN）帽直接接触，并且从p-FET器件去除对TiN帽有选择性的TiAlC层。 去除TiAlC层包括使用具有基本上高的TiAlC至TiN蚀刻比的选择性TiAlC至TiN湿蚀刻化学溶液，使得TiN帽保留在p-FET器件中。

公开(公告)号：US09905476B2

公开(公告)日：2018-02-27

申请号：US15412598

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/11 ,  H01L29/43 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

公开(公告)号：US09553092B2

公开(公告)日：2017-01-24

申请号：US14738288

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

Abstract translation: 通过直接金属栅极图案化在栅极腔中形成多个栅极叠层部分，以提供具有不同阈值电压的FinFET。 通过在不同的栅堆叠部分中选择性地并入具有不同功函数的金属层来获得不同的阈值电压。

公开(公告)号：US09589806B1

公开(公告)日：2017-03-07

申请号：US14886424

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Huihang Dong ,  John A. Fitzsimmons

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/283 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.

Abstract translation: 一种IC结构，包括：用于pFET的第一替换栅极堆叠，所述第一替换栅极堆叠包括：在所述介电层中的第一开口中的界面层; 在第一开口的界面层上的高k层; 在第一开口中的高k层上的pFET功函数金属层; 以及在pFET功函数金属层上方的基本上填充第一开口的第一栅极电极层; 以及用于nFET的第二替代栅极堆叠，所述第二栅极堆叠横向邻近所述第一栅极堆叠并且包括：所述介电层中的第二开口中的界面层; 在第二开口的界面层上的高k层; 在第二开口的高k层上的nFET功函数金属层; 以及在nFET功函数金属层上方的第二栅电极层，并基本上填充第二开口。

公开(公告)号：US20180254331A1

公开(公告)日：2018-09-06

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/3105 ,  H01L21/31053 ,  H01L29/6656

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

公开(公告)号：US20170133278A1

公开(公告)日：2017-05-11

申请号：US15412598

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L27/11 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.