公开(公告)号：US10699949B2

公开(公告)日：2020-06-30

申请号：US16379066

申请日：2019-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith Kwong Hon Wong ,  Wonwoo Kim ,  Praneet Adusumilli

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/485 ,  H01L21/285 ,  H01L23/532

Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.

公开(公告)号：US20190103310A1

公开(公告)日：2019-04-04

申请号：US15724431

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jim Shih-Chun LIANG ,  Keith Kwong Hon Wong

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76873 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L2924/01029

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.

公开(公告)号：US10096609B2

公开(公告)日：2018-10-09

申请号：US14622997

申请日：2015-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas L. Breil ,  Domingo A. Ferrer ,  Keith Kwong Hon Wong

IPC: H01L23/525 ,  H01L27/112 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

公开(公告)号：US09905476B2

公开(公告)日：2018-02-27

申请号：US15412598

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/11 ,  H01L29/43 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

公开(公告)号：US20170154687A1

公开(公告)日：2017-06-01

申请号：US14954151

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhigang Song ,  Oliver D. Patterson ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC: G11C29/04 ,  H01L21/768 ,  H01L23/58 ,  H01L21/66 ,  H01L27/11 ,  H01L27/108

CPC classification number: G11C29/04 ,  G11C29/025 ,  G11C29/56008 ,  G11C2029/0403 ,  G11C2029/5602 ,  H01L22/12 ,  H01L22/14 ,  H01L22/30 ,  H01L23/585 ,  H01L27/1104

Abstract: A SRAM-like electron beam inspection (EBI) structure and method for determining defects in integrated circuits inline during the production process at a level that enables earlier detection during fabrication. Initial layers, such as active layer, poly gate and contact of an IC are first fabricated, and a conductive mesh with horizontal components is provided above the contact layers connecting contact nodes of the contact layers. Voltage contrast is observed during EBI to detect short-circuits, open-circuits, or leakage currents formed between the horizontal components of the conductive mesh and metallized islands placed therebetween.

公开(公告)号：US09553092B2

公开(公告)日：2017-01-24

申请号：US14738288

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

Abstract translation: 通过直接金属栅极图案化在栅极腔中形成多个栅极叠层部分，以提供具有不同阈值电压的FinFET。 通过在不同的栅堆叠部分中选择性地并入具有不同功函数的金属层来获得不同的阈值电压。

公开(公告)号：US09337334B2

公开(公告)日：2016-05-10

申请号：US14257395

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hari V. Mallela ,  Edward J. Nowak ,  Yunsheng Song ,  Reinaldo A. Vega ,  Keith Kwong Hon Wong ,  Zhijian Yang

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H03K17/687 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L21/28026 ,  H01L21/28291 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/49 ,  H01L29/516 ,  H01L29/66568 ,  H01L29/6684 ,  H03K17/687

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract translation: 提供了包括沟道区和铁磁栅的半导体存储器件。 沟道区可以形成在半导体纳米线内。 铁磁栅极通过在一个方向上通过沟道区域的电流以选定的磁化取向来编程。 可以通过使用铁磁栅极作为栅电极的场效应晶体管的阈值电压的变化来检测铁磁栅极中的磁化方向，或者可以通过随着取向的变化而改变的沟道区域的电阻来检测 二端装置的磁化。

公开(公告)号：US09337289B2

公开(公告)日：2016-05-10

申请号：US14571628

申请日：2014-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

公开(公告)号：US10347529B2

公开(公告)日：2019-07-09

申请号：US15724431

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jim Shih-Chun Liang ,  Keith Kwong Hon Wong

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.