Invention Grant
- Patent Title: Gate height uniformity in semiconductor devices
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Application No.: US14730887Application Date: 2015-06-04
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Publication No.: US09349814B2Publication Date: 2016-05-24
- Inventor: Tsung-Liang Chen , Hung-Wei Liu , Rohit Pal , Hsin-Neng Tai , Huey-Ming Wang , Tae Hoon Lee , Songkram Srivathanakul , Danni Chen
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley and Mesiti PC
- Agent Nicholas Mesiti
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/423 ; H01L21/8238 ; H01L27/092

Abstract:
Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
Public/Granted literature
- US20150270364A1 GATE HEIGHT UNIFORMITY IN SEMICONDUCTOR DEVICES Public/Granted day:2015-09-24
Information query
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