公开(公告)号：US20170338325A1

公开(公告)日：2017-11-23

申请号：US15160845

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy Cao ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Songkram Srivathanakul

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31055 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/78

Abstract: We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer; and an ultraviolet (UV) cured high density plasma (HDP) nitride cap layer in the gate structure cavity above the at least one metal layer. We also disclose at least one method and at least one system by which the semiconductor device may be formed. The UV cured HDP nitride cap layer may be substantially free of voids or seams, and as a result, the semiconductor device may have a reduced Vt shift relative to comparable semiconductor devices known in the art.

公开(公告)号：US09130019B2

公开(公告)日：2015-09-08

申请号：US14150260

申请日：2014-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Huang Liu ,  Garo Jacques Derderian ,  Boaz Alperson

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/482

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract translation: 提供电路结构的导电接触结构及其制造方法。 该制造包括例如提供设置在半导体衬底上的至少一个接触开口; 形成包含含碳物质和设置在其中的元素碳的富碳接触衬垫材料，所述含碳物质和所述元素碳一起限定所述富碳接触衬里材料内的固定碳含量; 以及将所述富碳接触衬垫材料共形地沉积在设置在所述半导体衬底上的所述至少一个接触开口内。

公开(公告)号：US09093560B2

公开(公告)日：2015-07-28

申请号：US14032740

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L21/31 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract translation: 提供了通过控制由这些方法形成的介电材料和半导体器件的凹陷来促进栅极高度均匀性的方法。 所述方法包括例如用n型晶体管和p型晶体管形成半导体器件的晶体管，n型晶体管和p型晶体管包括多个牺牲栅极结构和在上表面处的保护掩模 的多个牺牲栅极结构; 在多个牺牲栅极结构之上和之间提供电介质材料; 部分致密化介电材料以形成部分致密化的电介质材料; 进一步致密化部分致密化的介电材料以产生改性的介电材料; 以及在改性介电材料上形成基本平坦的表面，以控制电介质材料凹陷和栅极高度。

公开(公告)号：US20140175562A1

公开(公告)日：2014-06-26

申请号：US13727218

申请日：2012-12-26

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Haiting Wang ,  Huang Liu ,  Yong Meng Lee ,  Songkram Srivathanakul

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/76837 ,  H01L21/823468 ,  H01L21/823864

Abstract: A semiconductor structure in fabrication includes a NFET and a PFET. Spacers adjacent gate structures of the NFET and PFET have undesired divots that can lead to substrate damage from chemicals used in a subsequent etch. The fabrication also leaves hard masks over the gate structures with non-uniform height. The divots are filled with material resistant to the chemicals used in the etch. Excess filler is removed, and uniform height is restored. Further fabrication may then proceed.

Abstract translation: 制造中的半导体结构包括NFET和PFET。 NFET和PFET的相邻栅极结构的间隔具有不期望的凹陷，这可能导致在后续蚀刻中使用的化学品的基底损伤。 该制造也在具有不均匀高度的门结构上留下硬掩模。 这些图案填充有耐蚀刻中使用的化学品的材料。 去除多余的填料，恢复均匀的高度。 然后进一步制造。

公开(公告)号：US09318440B2

公开(公告)日：2016-04-19

申请号：US14799116

申请日：2015-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Huang Liu ,  Garo Jacques Derderian ,  Boaz Alperson

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract translation: 提供电路结构的导电接触结构及其制造方法。 该制造包括例如提供设置在半导体衬底上的至少一个接触开口; 在所述半导体衬底上设置的所述至少一个接触开口中形成具有固定碳含量的富碳接触衬垫材料。

公开(公告)号：US08900940B2

公开(公告)日：2014-12-02

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/338 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US20180005893A1

公开(公告)日：2018-01-04

申请号：US15703601

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Huang Liu ,  Guillaume Bouche ,  Songkram Srivathanakul

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823821 ,  H01L29/66795

Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate. A patterned mask layer is formed above the process layer. The patterned mask layer includes first openings exposing portions of the process layer. A carbon-containing silicon dioxide layer is formed above the patterned mask layer and in the first openings. The carbon-containing silicon dioxide layer is planarized to remove portions extending outside the first openings and generate a plurality of mask elements from remaining portions of the carbon-containing silicon dioxide layer. The patterned mask layer is removed. The process layer is etched using the mask elements as an etch mask.

公开(公告)号：US09330982B1

公开(公告)日：2016-05-03

申请号：US14826276

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Songkram Srivathanakul ,  Jinping Liu ,  In Soo Jung

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/2255 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of forming a diffusion barrier film over fins and the resulting device are provided. Embodiments include forming silicon fins over a substrate; depositing a borosilicate glass (BSG) liner cap over a first set of the silicon fins; depositing a phosphosilicate (PSG) liner cap over a second set of the silicon fins; and depositing a silicon oxycarbide (SiOC) diffusion barrier film over the BSG and PSG liner caps.

Abstract translation: 提供了一种在翅片上形成扩散阻挡膜的方法和所得到的器件。 实施例包括在衬底上形成硅散热片; 在第一组硅片上沉积硼硅酸盐玻璃（BSG）衬垫帽; 在第二组硅片上沉积磷硅酸盐（PSG）衬垫帽; 并在BSG和PSG衬套上沉积硅碳氧化物（SiOC）扩散阻挡膜。

公开(公告)号：US20140193957A1

公开(公告)日：2014-07-10

申请号：US13738270

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish K. Jha ,  Tae-Hoon Kim ,  Tae Hoon Lee ,  Chang Ho Maeng ,  Songkram Srivathanakul ,  Haiting Wang

IPC: H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

Abstract translation: 通常，本发明的方面涉及用于形成半导体器件（例如具有降低的栅叠层高度差异的FET）的方法。 具体地，当在一组栅极堆叠之间检测/识别栅堆叠高度方差时，从不均匀栅极堆叠中去除硬掩模层和隔离层组，留下（尤其是）一组虚拟栅极。 衬套层和层间电介质形成在该组虚拟栅极上。 然后将衬垫层从该组虚拟栅极的顶表面（或其至少一部分）移除，然后去除该组虚拟栅极。 结果是具有较小高度变化/差异的一组栅极区域。

公开(公告)号：US08716150B1

公开(公告)日：2014-05-06

申请号：US13860603

申请日：2013-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Songkram Srivathanakul ,  Huang Liu ,  Hung-Wei Liu

IPC: H01L21/469 ,  H01L21/31

CPC classification number: H01L21/3105 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0234

Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

Abstract translation: 提供了形成半导体器件的方法。 所述方法包括例如形成具有连续平坦表面的低k电介质，并且在形成低k电介质之后，使低k电介质的连续平面表面经受乙烯等离子体增强化学气相沉积（PECVD ）治疗。