公开(公告)号：US09349814B2

公开(公告)日：2016-05-24

申请号：US14730887

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

公开(公告)号：US09093560B2

公开(公告)日：2015-07-28

申请号：US14032740

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang Chen ,  Hung-Wei Liu ,  Rohit Pal ,  Hsin-Neng Tai ,  Huey-Ming Wang ,  Tae Hoon Lee ,  Songkram Srivathanakul ,  Danni Chen

IPC: H01L21/31 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract translation: 提供了通过控制由这些方法形成的介电材料和半导体器件的凹陷来促进栅极高度均匀性的方法。 所述方法包括例如用n型晶体管和p型晶体管形成半导体器件的晶体管，n型晶体管和p型晶体管包括多个牺牲栅极结构和在上表面处的保护掩模 的多个牺牲栅极结构; 在多个牺牲栅极结构之上和之间提供电介质材料; 部分致密化介电材料以形成部分致密化的电介质材料; 进一步致密化部分致密化的介电材料以产生改性的介电材料; 以及在改性介电材料上形成基本平坦的表面，以控制电介质材料凹陷和栅极高度。

公开(公告)号：US09184288B2

公开(公告)日：2015-11-10

申请号：US14207822

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Zhiguo Sun ,  Sandeep Gaan ,  Danni Chen ,  Wen-Pin Peng ,  Huang Liu

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Abstract translation: 提供半导体结构和制造方法，其具有桥接膜，其有助于介电材料的下层和上覆的应力诱导层的粘附。 该方法包括例如在半导体衬底上提供其中设置有至少一个栅极结构的电介质材料层; 在所述介​​电材料层上提供具有所述至少一个栅极结构的桥接膜; 并在桥接膜上提供应力诱导层。 选择桥接膜以便于通过部分地与电介质材料层形成化学键而使介电材料的下层和上覆的应力诱导层两者粘附，而不与应力诱导层形成化学键 。