Invention Grant
- Patent Title: Techniques for forming contacts to quantum well transistors
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Application No.: US14334636Application Date: 2014-07-17
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Publication No.: US09356099B2Publication Date: 2016-05-31
- Inventor: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
- Applicant: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/41 ; H01L29/78 ; H01L29/66 ; H01L29/778 ; H01L29/775 ; H01L29/417 ; H01L29/423 ; H01L29/51

Abstract:
Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
Public/Granted literature
- US20140326953A1 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS Public/Granted day:2014-11-06
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