Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.