Invention Grant
- Patent Title: Configuration for power reduction in DRAM
- Patent Title (中): DRAM中功耗降低配置
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Application No.: US14327127Application Date: 2014-07-09
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Publication No.: US09361970B2Publication Date: 2016-06-07
- Inventor: Andre Schaefer , John B. Halbert
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C11/4074 ; G11C8/14 ; G11C11/408 ; G11C8/08 ; G11C11/404 ; G06F1/32
Abstract:
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.
Public/Granted literature
- US20140325136A1 CONFIGURATION FOR POWER REDUCTION IN DRAM Public/Granted day:2014-10-30
Information query
