公开(公告)号：US10949296B2

公开(公告)日：2021-03-16

申请号：US15681387

申请日：2017-08-20

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/42 ,  G11C29/44 ,  G11C11/40 ,  G11C29/04 ,  G11C29/56

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

公开(公告)号：US10109340B2

公开(公告)日：2018-10-23

申请号：US15639725

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Nadav Bonen ,  Tomer Levy

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

公开(公告)号：US09865326B2

公开(公告)日：2018-01-09

申请号：US15363399

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

IPC: G06F13/10 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06

CPC classification number: G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US09704544B2

公开(公告)日：2017-07-11

申请号：US15360675

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Bruce A. Christenson ,  Kuljit S. Bains

IPC: G06F12/00 ,  G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

公开(公告)号：US10572343B2

公开(公告)日：2020-02-25

申请号：US15873357

申请日：2018-01-17

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kjersten E. Criss

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.

公开(公告)号：US10108512B2

公开(公告)日：2018-10-23

申请号：US15089316

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/22 ,  G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: Embodiments are generally directed to validation of memory on-die error correction code. An embodiment of a memory device includes one or more memory arrays for the storage of data; control logic to control operation of the memory device; and ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays. In a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.

公开(公告)号：US10083737B2

公开(公告)日：2018-09-25

申请号：US15633604

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C11/4078 ,  G06F13/16 ,  G11C11/406 ,  G11C11/408 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

公开(公告)号：US09761298B2

公开(公告)日：2017-09-12

申请号：US15364123

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G06F3/06 ,  G06F12/06

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

公开(公告)号：US20170060681A1

公开(公告)日：2017-03-02

申请号：US14998184

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Abstract translation: 错误检查和擦除（ECS）模式使存储器件能够执行错误检查和校正（ECC）并计数错误。 相关联的存储器控​​制器通过触发发送到存储器件的触发器来触发ECS模式。 存储器件包括多个可寻址的存储器位置，其可以被组织成诸如字线的段。 存储器位置存储数据并具有相关联的ECC信息。 在ECS模式中，存储器件读取一个或多个存储器位置，并且基于ECC信息为一个或多个存储器位置执行ECC。 存储器装置对包括指示具有至少阈值数量的错误的段的数量的段计数以及指示任何段中的最大错误数的最大计数的错误信息进行计数。

公开(公告)号：US09564201B2

公开(公告)日：2017-02-07

申请号：US15011286

申请日：2016-01-29

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G11C11/4076 ,  G06F12/06 ,  G11C7/10

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。