Invention Grant
US09363071B2 Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
有权
从多条有线数据信号恢复时钟信号的电路，每个状态周期发生变化状态，并且免受数据通道间偏移以及数据状态转换毛刺
- Patent Title: Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
- Patent Title (中): 从多条有线数据信号恢复时钟信号的电路，每个状态周期发生变化状态，并且免受数据通道间偏移以及数据状态转换毛刺
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Application No.: US14199322Application Date: 2014-03-06
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Publication No.: US09363071B2Publication Date: 2016-06-07
- Inventor: Shoichiro Sengoku , Chulkyu Lee , George Alan Wiley , Joseph Cheung
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H04B3/00
- IPC: H04B3/00 ; H04L7/033 ; H04L7/027 ; H04L7/00 ; H04L25/49 ; H04L25/493 ; H03K5/1252 ; H03K5/1534 ; H04L25/14 ; H04L25/02
Abstract:
A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.
Public/Granted literature
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