Invention Grant
- Patent Title: Optimizing power usage by factoring processor architectural events to PMU
-
Application No.: US14598454Application Date: 2015-01-16
-
Publication No.: US09367112B2Publication Date: 2016-06-14
- Inventor: Yen-Cheng Liu , P. Keong Or , Krishnakanth V. Sistla , Ganapati Srinivasa
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/20
Abstract:
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
Public/Granted literature
- US20150127962A1 OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU Public/Granted day:2015-05-07
Information query
