Invention Grant
US09367497B2 Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus 有权
可重构地指定与系统总线不同的边带通信线路上的条件输出的主核

Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus
Abstract:
A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.
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