Invention Grant
US09368168B2 Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same
有权
非易失性存储器件包括外围电路，以接收与信号的上升沿和下降沿中的一个同步的地址，而不管是选择第一还是第二对准类型，并且包括其的非易失性存储器系统
- Patent Title: Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same
- Patent Title (中): 非易失性存储器件包括外围电路，以接收与信号的上升沿和下降沿中的一个同步的地址，而不管是选择第一还是第二对准类型，并且包括其的非易失性存储器系统
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Application No.: US14856218Application Date: 2015-09-16
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Publication No.: US09368168B2Publication Date: 2016-06-14
- Inventor: Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-Si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2008-0017956 20080227; KR10-2008-0061767 20080627
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C16/32 ; G11C7/22 ; G11C16/10 ; G11C16/08 ; G11C16/26
Abstract:
A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Public/Granted literature
- US20160005483A1 FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME Public/Granted day:2016-01-07
Information query
