Invention Grant
- Patent Title: Low package parasitic inductance using a thru-substrate interposer
- Patent Title (中): 低封装寄生电感使用贯穿衬底插入器
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Application No.: US14020558Application Date: 2013-09-06
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Publication No.: US09370103B2Publication Date: 2016-06-14
- Inventor: Changhan Hobie Yun , Chengjie Zuo , Jonghae Kim , Daeik Daniel Kim , Mario Francisco Velez
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorported
- Current Assignee: QUALCOMM Incorported
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H05K1/18
- IPC: H05K1/18 ; H05K1/16 ; H05K1/03 ; H05K1/11 ; H05K3/46 ; H01L23/498 ; H01L23/50
Abstract:
An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).
Public/Granted literature
- US20150070863A1 LOW PACKAGE PARASITIC INDUCTANCE USING A THRU-SUBSTRATE INTERPOSER Public/Granted day:2015-03-12
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