公开(公告)号：US10262786B2

公开(公告)日：2019-04-16

申请号：US15288967

申请日：2016-10-07

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Babak Nejati ,  Husnu Ahmet Masaracioglu

IPC: H03H7/01 ,  H03H7/46 ,  H01F17/00 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H03H1/00

Abstract: A stepped-width, co-spiral inductor structure includes a first exterior layer having a first exterior width. The stepped-width, co-spiral inductor structure also includes a first interior layer coupled to the first exterior layer. The first interior layer includes a first interior width that is wider than the first exterior width of the first exterior layer. The stepped-width, co-spiral inductor structure further includes a second exterior layer coupled to the first interior layer. The second exterior layer includes a second exterior width that is narrower than the first interior width of the first interior layer.

公开(公告)号：US10187031B2

公开(公告)日：2019-01-22

申请号：US15151351

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H7/38 ,  H03H7/40 ,  H04B1/04

Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.

公开(公告)号：US10074625B2

公开(公告)日：2018-09-11

申请号：US14859323

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco Velez ,  David Francis Berdy ,  Changhan Hobie Yun ,  Jonghae Kim ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0905

Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.

公开(公告)号：US10069474B2

公开(公告)日：2018-09-04

申请号：US15137662

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy ,  Yunfei Ma ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H9/05 ,  H03H9/10 ,  H03H9/15 ,  H03H3/02 ,  H01F17/02 ,  H05K1/18 ,  H03H9/54 ,  H05K3/46 ,  H05K1/03 ,  H05K3/00 ,  H03H3/08 ,  H03H9/64 ,  H01F17/00 ,  H03H7/01 ,  H03H7/46

Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.

公开(公告)号：US10026546B2

公开(公告)日：2018-07-17

申请号：US15160776

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  David Francis Berdy

IPC: H03H7/46 ,  H01F27/40 ,  H01F27/28 ,  H01F27/29 ,  H01F41/02 ,  H03H7/01

Abstract: An apparatus includes a substrate and a three-dimensional (3D) wirewound inductor integrated within the substrate. The apparatus further includes a capacitor coupled to the 3D wirewound inductor.

公开(公告)号：US09692386B2

公开(公告)日：2017-06-27

申请号：US14177620

申请日：2014-02-11

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Mario Francisco Velez ,  Jonghae Kim ,  Daeik Daniel Kim ,  Changhan Hobie Yun

IPC: H03H7/01 ,  H01F27/28 ,  H01L23/522

CPC classification number: H03H7/0115 ,  H01F27/2866 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48464 ,  Y10T29/417 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An inductor is provided on a substrate that includes a capacitor. The inductor comprises a series of wire loops. An end of the wire loop is wire bonded to the capacitor.

公开(公告)号：US09502586B1

公开(公告)日：2016-11-22

申请号：US14853931

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Je-Hsiung Jeffrey Lan ,  Changhan Hobie Yun ,  Jonghae Kim

IPC: H01L29/93 ,  H01L27/108 ,  H01L21/70 ,  H01L27/08 ,  H01L29/66

CPC classification number: H01L27/0808 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/78 ,  H01L27/1203 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/93

Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

Abstract translation: 对称变容二极管结构可以包括第一变容二极管组件。 第一变容二极管分量可以包括作为第二板操作的栅极，作为电介质层工作的栅极氧化物层和作为区域调制电容器的第一板工作的主体。 此外，掺杂区域可围绕第一变容二极管部件的主体。 第一变容二极管组件可以由隔离层在背面支撑。 对称变容二极管结构还可以包括通过背侧导电层电耦合到第一变容二极管部件的背侧的第二变容二极管部件。

公开(公告)号：US09468098B2

公开(公告)日：2016-10-11

申请号：US14220913

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka

IPC: H01L23/538 ,  H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H01L23/48 ,  H01L23/64 ,  H05K1/02 ,  H05K3/36 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/19101 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/18 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/1003 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/1316 ,  Y10T29/4902 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract translation: 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。

公开(公告)号：US09384883B2

公开(公告)日：2016-07-05

申请号：US14155172

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Hobie Yun

IPC: H01F27/28 ,  H01F41/00 ,  H01F17/00

CPC classification number: H01F41/041 ,  H01F27/2804 ,  H01F41/00 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

Abstract translation: 3D嵌套变压器包括具有与一组迹线菊花链连接的一组通过衬底通孔的衬底。 至少一些直通衬底通孔具有第一和第二导电区域。 该组迹线还包括将至少一些贯穿衬底通孔的第一导电区域耦合在一起的第一组迹线，以及将至少一些第二导电区域连接在一起的穿过衬底通孔的第二组迹线。

公开(公告)号：US09368566B2

公开(公告)日：2016-06-14

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。