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公开(公告)号：US12016247B2
公开(公告)日：2024-06-18
申请号：US17005168
申请日：2020-08-27
发明人： Changhan Hobie Yun , Nosun Park , Daniel Daeik Kim , Paragkumar Ajaybhai Thadesar , Sameer Sunil Vadhavkar
CPC分类号： H10N30/1051 , H03H9/02015 , H03H9/02535
摘要： A package that includes an integrated device, an integrated passive device and a void. The integrated device is configured as a filter. The integrated device includes a substrate comprising a piezoelectric material, and at least one metal layer coupled to a first surface of the first substrate. The integrated passive device is coupled to the integrated device. The integrated passive device is configured as a cap for the integrated device. The void is located between the integrated device and the integrated passive device.
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公开(公告)号：US11502652B2
公开(公告)日：2022-11-15
申请号：US16870383
申请日：2020-05-08
发明人： Daniel Daeik Kim , Paragkumar Ajaybhai Thadesar , Changhan Hobie Yun , Sameer Sunil Vadhavkar , Nosun Park
摘要： A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.
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公开(公告)号：US10433425B1
公开(公告)日：2019-10-01
申请号：US16051876
申请日：2018-08-01
摘要： A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.
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公开(公告)号：US10361149B2
公开(公告)日：2019-07-23
申请号：US15233906
申请日：2016-08-10
发明人： Chengjie Zuo , Mario Francisco Velez , Changhan Hobie Yun , David Francis Berdy , Daeik Daniel Kim , Jonghae Kim
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56 , H01L23/15 , H01L23/31 , H01L23/14 , H01L23/00 , H05K1/02 , H01L23/64 , H05K3/34
摘要： A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.
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公开(公告)号：US10332911B2
公开(公告)日：2019-06-25
申请号：US15380800
申请日：2016-12-15
发明人： Shiqun Gu , Daeik Daniel Kim , Matthew Michael Nowak , Jonghae Kim , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , David Francis Berdy
IPC分类号： H01L21/84 , H01L23/66 , H01L27/12 , H01L29/10 , H01L29/66 , H01L21/304 , H01L21/306 , H01L21/762 , H01L21/768 , H01L23/498 , H01L23/528 , H01L27/088 , H01L27/092 , H01L21/8234
摘要： An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.
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公开(公告)号：US10332671B2
公开(公告)日：2019-06-25
申请号：US15345312
申请日：2016-11-07
发明人： Mario Francisco Velez , Niranjan Sunil Mudakatte , Changhan Hobie Yun , Daeik Daniel Kim , David Francis Berdy , Jonghae Kim , Yunfei Ma , Chengjie Zuo
IPC分类号： H04B5/00 , H01F27/02 , H01F27/28 , H01L23/31 , H01L23/00 , H01L21/56 , H01F27/29 , H01F41/06 , H01F38/14 , H01L23/522 , H01L23/64 , H01L25/16 , H01L49/02
摘要： An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.
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公开(公告)号：US10283257B2
公开(公告)日：2019-05-07
申请号：US14991803
申请日：2016-01-08
摘要： A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.
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公开(公告)号：US10103116B2
公开(公告)日：2018-10-16
申请号：US15077869
申请日：2016-03-22
发明人： Daeik Daniel Kim , Mario Francisco Velez , Changhan Hobie Yun , Chengjie Zuo , David Francis Berdy , Jonghae Kim , Niranjan Sunil Mudakatte
摘要： A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
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9.发明授权公开(公告)号：US09959964B2
公开(公告)日：2018-05-01
申请号：US14941493
申请日：2015-11-13
发明人： Changhan Hobie Yun , David Francis Berdy , Daeik Daniel Kim , Chengjie Zuo , Jonghae Kim , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Niranjan Sunil Mudakatte
CPC分类号： H01F10/12 , H01F17/0013 , H01F27/2804 , H01F41/042 , H01F41/046 , H01F2017/0066 , H01F2027/2809
摘要： A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.
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10.发明授权公开(公告)号：US09954267B2
公开(公告)日：2018-04-24
申请号：US15067106
申请日：2016-03-10
发明人： Changhan Hobie Yun , Daeik Daniel Kim , Mario Francisco Velez , Chengjie Zuo , David Francis Berdy , Jonghae Kim
CPC分类号： H01P5/16 , H01Q1/22 , H01Q1/50 , H03H7/0115 , H03H7/463
摘要： A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.
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