Invention Grant
- Patent Title: Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
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Application No.: US14841956Application Date: 2015-09-01
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Publication No.: US09372799B2Publication Date: 2016-06-21
- Inventor: Daniel B Wu , Matthew D Pierson , Kai Chirca , Timothy D Anderson
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frank D. Cimino
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F12/08 ; G06F13/16 ; G06F13/40

Abstract:
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
Public/Granted literature
- US20150370710A1 OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION Public/Granted day:2015-12-24
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