Invention Grant
US09373165B2 Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance
有权
增强的图案化晶圆几何测量基于设计改进，以实现最佳集成芯片制造性能
- Patent Title: Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance
- Patent Title (中): 增强的图案化晶圆几何测量基于设计改进，以实现最佳集成芯片制造性能
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Application No.: US14520998Application Date: 2014-10-22
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Publication No.: US09373165B2Publication Date: 2016-06-21
- Inventor: Amir Azordegan , Pradeep Vukkadala , Craig MacNaughton , Jaydeep Sinha
- Applicant: KLA-Tencor Corporation
- Applicant Address: US CA Milpitas
- Assignee: KLA-Tencor Corporation
- Current Assignee: KLA-Tencor Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Suiter Swantz pc llo
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06T7/00 ; G01B11/24 ; G01N21/95
Abstract:
Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.
Public/Granted literature
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