-
公开(公告)号：US10788759B2
公开(公告)日：2020-09-29
申请号：US16049266
申请日：2018-07-30
摘要： Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.
-
公开(公告)号：US10576603B2
公开(公告)日：2020-03-03
申请号：US14313733
申请日：2014-06-24
发明人： Pradeep Vukkadala , Jaydeep Sinha
摘要： Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.
-
公开(公告)号：US20180364579A1
公开(公告)日：2018-12-20
申请号：US16049266
申请日：2018-07-30
IPC分类号： G03F7/20
CPC分类号： G03F7/707 , G03F7/70783
摘要： Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.
-
公开(公告)号：US09702829B1
公开(公告)日：2017-07-11
申请号：US14246895
申请日：2014-04-07
发明人： Haiguang Chen , Jaydeep Sinha , Sergey Kamensky , Enrique Chavez , Shouhong Tang , Mark Plemmons
IPC分类号： G01B9/02 , G01N21/95 , G01N21/956 , G01B11/30
CPC分类号： G01N21/9501 , G01B11/30 , G01B11/303 , G01B11/306 , G01B2210/56 , G01N21/956
摘要： Interferometer systems and methods for providing improved defect detection and quantification are disclosed. The systems and methods in accordance with the present disclosure may detect surface defects on patterned or bare wafer surfaces and subsequently quantify them. In certain embodiments in accordance with the present disclosure, amplitude maps of the wafer surfaces are obtained and are utilized in addition/alternative to phase maps for wafer surface feature detection. Furthermore, local one-dimensional and/or two-dimensional unwrapping techniques are also disclosed and are utilized in certain embodiments in accordance with the present disclosure to provide height and depth information of the detected defects, further improving the detection capabilities of the measurement systems.
-
5.发明授权Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry 有权使用干涉测量预测和控制晶片中的关键尺寸问题和图案缺陷公开(公告)号：US09558545B2
公开(公告)日：2017-01-31
申请号：US14730997
申请日：2015-06-04
CPC分类号： G06T7/0004 , G06K9/6201 , G06T7/001 , G06T2207/10004 , G06T2207/30148 , H01L22/12 , H01L22/20
摘要： Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.
摘要翻译： 公开了使用图案化晶片几何（PWG）测量在图案化晶片中预测和控制图案质量数据（例如临界尺寸和/或图案缺陷率）的系统和方法。 可以建立PWG测量和模式质量数据测量之间的相关性，并且可以利用所建立的相关性来基于为给定晶片获得的几何测量来为给定晶片提供图案质量数据预测。 可以将所产生的预测提供给光刻工具，光刻工具可以利用预测来校正可能在光刻工艺期间发生的焦点和/或标题误差。
-
6.发明申请Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance 有权基于增强图案化晶圆几何测量的设计改进，优化集成芯片制造性能公开(公告)号：US20160071260A1
公开(公告)日：2016-03-10
申请号：US14520998
申请日：2014-10-22
CPC分类号： G01N21/9501 , G01B11/24 , G01N21/956 , G06T3/4069
摘要： Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.
摘要翻译： 公开了能够对图案化晶片进行超高分辨率地形测量的方法和系统。 可以利用超高分辨率测量获得的测量来提高晶片度量测量精度。 此外，利用超高分辨率度量获得的测量结果也可用于提供反馈和/或校准控制以改善晶片的制造和设计。
-
7.发明申请Process-Induced Distortion Prediction and Feedforward and Feedback Correction of Overlay Errors 审中-公开过程诱导的失真预测和覆盖误差的前馈和反馈校正公开(公告)号：US20150120216A1
公开(公告)日：2015-04-30
申请号：US14490408
申请日：2014-09-18
CPC分类号： G01N19/08 , C23C14/54 , G01L1/00 , G01L5/0047 , G03F7/705 , G03F7/70633 , G03F7/70783 , H01L22/12 , H01L22/20
摘要： Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
摘要翻译： 公开了用于预测和测量重叠误差的系统和方法。 可以使用基于薄膜力的计算力学模型来预测或测量过程引起的重叠误差。 更具体地，关于膜力的分布的信息被提供给有限元（FE）模型，以在存在复应力模式的情况下提供更准确的逐点预测。 还公开了晶片几何感应重叠误差的增强预测和测量。
-
公开(公告)号：US20190271654A1
公开(公告)日：2019-09-05
申请号：US15406732
申请日：2017-01-15
摘要： Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.
-
公开(公告)号：US10025894B2
公开(公告)日：2018-07-17
申请号：US15172667
申请日：2016-06-03
摘要： Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.
-
10.发明授权公开(公告)号：US09779202B2
公开(公告)日：2017-10-03
申请号：US14867226
申请日：2015-09-28
发明人： Pradeep Vukkadala , Jaydeep Sinha , Jong-Hoon Kim
CPC分类号： G06F17/5081 , G03F1/44 , G03F7/705 , G03F7/70633 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.018 秒)