Invention Grant
US09373583B2 High quality factor filter implemented in wafer level packaging (WLP) integrated device
有权
高品质因子滤波器在晶圆级封装(WLP)集成器件中实现
- Patent Title: High quality factor filter implemented in wafer level packaging (WLP) integrated device
- Patent Title (中): 高品质因子滤波器在晶圆级封装(WLP)集成器件中实现
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Application No.: US14323907Application Date: 2014-07-03
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Publication No.: US09373583B2Publication Date: 2016-06-21
- Inventor: Jong-Hoon Lee , Young Kyu Song , Jung Ho Yoon , Uei Ming Jow , Xiaonan Zhang , Ryan David Lane
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L23/522 ; H01L49/02 ; H01L23/64 ; H01L25/065 ; H01L25/07 ; H01L25/11 ; H01L23/00 ; H01L25/03 ; H01L23/525

Abstract:
Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.
Public/Granted literature
- US20140319652A1 HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE Public/Granted day:2014-10-30
Information query
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