公开(公告)号：US09653533B2

公开(公告)日：2017-05-16

申请号：US14625484

申请日：2015-02-18

申请人： QUALCOMM Incorporated

发明人： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang

IPC分类号： H01L23/52 ,  H01L49/02 ,  H01L23/522 ,  H01G4/33 ,  H01L23/64

CPC分类号： H01L28/86 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60

摘要： An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

公开(公告)号：US20160372253A1

公开(公告)日：2016-12-22

申请号：US14746652

申请日：2015-06-22

申请人： QUALCOMM Incorporated

发明人： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Jung Ho Yoon ,  Sangjo Choi ,  Xiaonan Zhang

IPC分类号： H01F27/28 ,  H01F41/04

CPC分类号： H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F41/041 ,  H01F2027/2809

摘要： An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

摘要翻译： 电感器结构包括对应于电感器的第一层的第一组迹线，对应于电感器的第二层的第二组迹线，以及对应于电感器的第三层的第三组迹线，其位于 第一层和第二层。 第一组轨迹包括与第一轨迹平行的第一轨迹和第二轨迹。 第一个跟踪的维度与第二个跟踪的相应维度不同。 第二组迹线耦合到第一组迹线。 第二组迹线包括耦合到第一迹线和第二迹线的第三迹线。 第三组迹线耦合到第一组迹线。

公开(公告)号：US09449762B2

公开(公告)日：2016-09-20

申请号：US14272356

申请日：2014-05-07

申请人： QUALCOMM Incorporated

发明人： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC分类号： H05K1/03 ,  H01G4/236 ,  H01G2/02 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H05K3/46 ,  H01G2/10 ,  H05K1/02

CPC分类号： H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

摘要： Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

摘要翻译： 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20160240463A1

公开(公告)日：2016-08-18

申请号：US14703290

申请日：2015-05-04

申请人： QUALCOMM Incorporated

发明人： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

摘要： An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

摘要翻译： 一种集成电路器件，包括封装衬底和耦合到封装衬底的管芯。 封装衬底包括至少一个电介质层，至少一个电介质层中的第一互连的第一叠层，以及形成在所述至少一个电介质层的至少一个侧部上的第二互连。 第一互连的第一堆叠被配置为提供用于非接地参考信号的第一电路径，其中第一互连的第一堆叠沿着封装衬底的至少一侧设置。 第二互连被配置为提供用于接地参考信号的第二电路径。

公开(公告)号：US20150115403A1

公开(公告)日：2015-04-30

申请号：US14063934

申请日：2013-10-25

申请人： QUALCOMM Incorporated

发明人： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC分类号： H01L49/02

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

摘要翻译： 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。

公开(公告)号：US10051741B2

公开(公告)日：2018-08-14

申请号：US14073756

申请日：2013-11-06

申请人： QUALCOMM Incorporated

发明人： Young Kyu Song ,  Daeik Daniel Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Jonghae Kim

IPC分类号： H05K1/18 ,  H05K1/16 ,  H05K1/14

摘要： An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

公开(公告)号：US09362218B2

公开(公告)日：2016-06-07

申请号：US13968627

申请日：2013-08-16

申请人： QUALCOMM Incorporated

发明人： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L49/02 ,  H01L23/50 ,  H01L23/64 ,  H01L23/522

CPC分类号： H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

摘要： Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

摘要翻译： 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US20150237732A1

公开(公告)日：2015-08-20

申请号：US14200684

申请日：2014-03-07

申请人： QUALCOMM Incorporated

发明人： Mario Francisco Velez ,  Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo

IPC分类号： H05K1/18 ,  H01L21/48 ,  H05K3/40 ,  H05K1/03 ,  H05K1/16 ,  H01L23/498 ,  H05K1/11

CPC分类号： H05K1/182 ,  H01F17/0006 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/10 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/10242 ,  H05K2201/10984 ,  Y10T29/49165

摘要： A low-profile passive-on-package is provided that includes a plurality of recesses that receive corresponding interconnects. Because of the receipt of the interconnects in the recesses, the passive-on-package has a height that is less than a sum of a thickness for the substrate and an interconnect height or diameter.

摘要翻译： 提供了一种低调无源封装，其包括接收相应互连的多个凹槽。 由于在凹槽中接收到互连，所以被动封装的高度小于衬底的厚度和互连高度或直径的总和。

公开(公告)号：US20150130021A1

公开(公告)日：2015-05-14

申请号：US14079488

申请日：2013-11-13

申请人： QUALCOMM Incorporated

发明人： Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim

IPC分类号： H01L49/02

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/0053

摘要： Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

摘要翻译： 一些实施方式提供了一种集成器件（例如，半导体器件），其包括衬底中的衬底和电感器。 在一些实施方案中，电感器是螺线管电感器。 电感器包括一组绕组。 该组绕组具有内周。 该组绕组包括一组互连和一组通孔。 该组互连和一组通孔位于该组绕组的内周边之外。 在一些实施方案中，该组绕组还包括一组捕获垫。 该组互连通过一组捕获垫耦合到该组通孔。 在一些实施方式中，该组绕组具有外周边。 该组焊盘耦合到该组互连件，使得该组焊盘至少部分地位于该组绕组的外周边之外。

公开(公告)号：US20150092314A1

公开(公告)日：2015-04-02

申请号：US14039192

申请日：2013-09-27

申请人： QUALCOMM Incorporated

发明人： Daeik Daniel Kim ,  Young Kyu Song ,  Mario Francisco Velez ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Xiaonan Zhang ,  Ryan David Lane ,  Matthew Michael Nowak

IPC分类号： H01F27/29 ,  H01F41/04 ,  H01F27/40

CPC分类号： H01F27/29 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/002 ,  H01F2017/0073 ,  Y10T29/4902

摘要： A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

摘要翻译： 系统包括耦合到衬底的第一表面的第一连接器。 第一连接器使得系统能够电耦合到衬底外部的第一器件。 该系统包括耦合到基板的第二表面的第二连接器。 该系统还包括从第一表面延伸穿过基底的多个导电通孔到第二表面。 多个导电通孔围绕第一连接器和第二连接器。 多个导电通孔电耦合在一起以形成环形电感器。 环形电感器的第一引线电耦合到第一连接器。 环形电感器的第二引线电耦合到第二连接器。