An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.