Invention Grant
US09385699B2 Delay cell, delay locked look circuit, and phase locked loop circuit
有权
延迟单元，延迟锁定外观电路和锁相环电路
- Patent Title: Delay cell, delay locked look circuit, and phase locked loop circuit
- Patent Title (中): 延迟单元，延迟锁定外观电路和锁相环电路
-
Application No.: US14719406Application Date: 2015-05-22
-
Publication No.: US09385699B2Publication Date: 2016-07-05
- Inventor: Dong-Hyuk Lim , Jae-Jin Park , Seung-Hoon Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2014-0094155 20140724
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03K5/135 ; H03L7/081 ; H03K5/00
Abstract:
A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell.
Public/Granted literature
- US20160028410A1 DELAY CELL, DELAY LOCKED LOOK CIRCUIT, AND PHASE LOCKED LOOP CIRCUIT Public/Granted day:2016-01-28
Information query
