公开(公告)号：US09385699B2

公开(公告)日：2016-07-05

申请号：US14719406

申请日：2015-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk Lim ,  Jae-Jin Park ,  Seung-Hoon Lee

IPC: H03L7/06 ,  H03K5/135 ,  H03L7/081 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00013 ,  H03L7/0812

Abstract: A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell.

Abstract translation: 延迟单元包括第一晶体管和第二晶体管，其中至少一个具有完全耗尽的绝缘体上硅（FD-SOI）结构。 第一控制电压被施加到第一晶体管的主体，并且第二控制电压被施加到第二晶体管的主体，以便调整延迟单元的延迟时间。 DLL和PLL电路包括这种类型的延迟单元。

公开(公告)号：US09893721B2

公开(公告)日：2018-02-13

申请号：US15206384

申请日：2016-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Seok Lee ,  Woo-Seok Kim ,  Jae-Jin Park ,  Dong-Hyuk Lim ,  Dae-Young Chung

IPC: H03K5/1534 ,  H04L7/00 ,  H03K19/21 ,  H01L27/118

CPC classification number: H03K5/1534 ,  G01R31/00 ,  H01L27/11803 ,  H01L28/00 ,  H01L2027/11881 ,  H03K19/21 ,  H04L1/00 ,  H04L7/0037 ,  H04L7/0087

Abstract: An edge detector includes a differential signal generator, a sense amplifier and a latch. The differential signal generator delays an input signal to generate a first differential signal and inverts the input signal to generate a second differential signal. The sense amplifier amplifies a difference between the first differential signal and the second differential signal to generate a first amplification signal and a second amplification signal at a first edge of a test clock signal and resets the first amplification signal and the second amplification signal at a second edge of the test clock signal. The latch generates an edge signal corresponding to edge information of the input signal in response to the first amplification signal and the second amplification signal.

公开(公告)号：US09632126B2

公开(公告)日：2017-04-25

申请号：US14526849

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kun-Yong Yoon ,  Jae-Jin Park ,  Ji-Hwan Hyun

IPC: G05F5/00 ,  G01R31/02 ,  G01R31/28

CPC classification number: G01R31/025 ,  G01R31/2851

Abstract: An integrated circuit includes an operational circuit and a test circuit for measuring a leakage current associated with all or part of the operational circuit. The leakage current measurement circuit may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.

公开(公告)号：US10698013B2

公开(公告)日：2020-06-30

申请号：US15360196

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Young Chung ,  Jae-Jin Park ,  Dong-Hyuk Lim

IPC: G01R19/00 ,  G01R23/02 ,  H03D3/00 ,  H03F3/45 ,  H03D7/12 ,  H03F3/04 ,  H03K5/02

Abstract: A lock-in amplifier includes a clock signal generator configured to generate a first demodulation clock signal and a second demodulation clock signal having a phase difference of 90 degrees and a same demodulation frequency; and a detector configured to, based on an input signal, the first demodulation clock signal, and the second demodulation clock signal, provide an offset voltage corresponding to an offset of the lock-in amplifier in a first operation mode, and provide a first output voltage and a second output voltage, each of which correspond to a demodulation frequency component of the input signal in a second operation mode.

公开(公告)号：US20150233996A1

公开(公告)日：2015-08-20

申请号：US14526849

申请日：2014-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kun-Yong Yoon ,  Jae-Jin Park ,  Ji-Hwan Hyun

IPC: G01R31/02 ,  G01R31/28 ,  G01R1/30

CPC classification number: G01R31/025 ,  G01R31/2851

Abstract: An integrated circuit includes an operational circuit and a test circuit for measuring a leakage current associated with all or part of the operational circuit. The leakage current measurement circuit may include a mirror circuit configured to mirror leakage current to a current-to-voltage converter and an analog-to-digital converter configured to convert the analog voltage representative of the leakage current developed by the current-to-voltage converter to a digital value.

Abstract translation: 集成电路包括用于测量与全部或部分操作电路相关联的漏电流的操作电路和测试电路。 泄漏电流测量电路可以包括被配置为将漏电流镜像到电流 - 电压转换器的镜电路和被配置为转换表示由电流 - 电压产生的漏电流的模拟电压的模数转换器 转换器到数字值。