Invention Grant
US09397167B2 Nitride semiconductor wafer, nitride semiconductor device, and method for manufacturing nitride semiconductor wafer
有权
氮化物半导体晶片，氮化物半导体器件以及氮化物半导体晶片的制造方法
- Patent Title: Nitride semiconductor wafer, nitride semiconductor device, and method for manufacturing nitride semiconductor wafer
- Patent Title (中): 氮化物半导体晶片，氮化物半导体器件以及氮化物半导体晶片的制造方法
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Application No.: US13729713Application Date: 2012-12-28
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Publication No.: US09397167B2Publication Date: 2016-07-19
- Inventor: Hisashi Yoshida , Toshiki Hikosaka , Yoshiyuki Harada , Naoharu Sugiyama , Shinya Nunoue
- Applicant: Hisashi Yoshida , Toshiki Hikosaka , Yoshiyuki Harada , Naoharu Sugiyama , Shinya Nunoue
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-212884 20120926
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/20 ; H01L21/02 ; H01L29/778 ; H01L29/06 ; H01L33/00 ; H01L33/12
Abstract:
A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.
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