Invention Grant
- Patent Title: On-chip traffic prioritization in memory
- Patent Title (中): 内存中的片上流量优先级
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Application No.: US13737339Application Date: 2013-01-09
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Publication No.: US09405711B2Publication Date: 2016-08-02
- Inventor: Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/18 ; G06F9/48 ; G06F13/16

Abstract:
According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.
Public/Granted literature
- US20140195743A1 ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY Public/Granted day:2014-07-10
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