公开(公告)号：US10007242B2

公开(公告)日：2018-06-26

申请号：US14736758

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Bryan S. Rosenburg

IPC: G05B15/02

CPC classification number: G05B15/02

Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.

公开(公告)号：US09841926B2

公开(公告)日：2017-12-12

申请号：US15198868

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/18 ,  G06F13/16 ,  G06F9/48

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

公开(公告)号：US09632559B2

公开(公告)日：2017-04-25

申请号：US15137184

申请日：2016-04-25

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Augusto J. Vega

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/46

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

Abstract: Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.

公开(公告)号：US09389675B2

公开(公告)日：2016-07-12

申请号：US14133861

申请日：2013-12-19

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Augusto J. Vega

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the power cap, actions are performed including: reducing power provided to a first power-consuming component based on determining that it has an activity level below a first threshold and that power can be reduced to the first power-consuming component. Power provided to a second power-consuming component is reduced based on determining that it has an activity level below a second threshold and that power can be reduced to the second power-consuming component. Power reduction is forced in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component.

Abstract translation: 根据一个实施例，提供了一种用于包括至少两个功耗组件的计算节点的功率管理的方法。 功率上限控制系统将计算节点的功耗级别与功率上限进行比较。 基于确定功耗水平大于功率上限，执行动作，包括：基于确定其具有低于第一阈值的活动水平并且该功率可以减小到第一功耗组件来提供的功率 第一个耗电量的组件。 基于确定其具有低于第二阈值的活动水平并且该功率可以减小到第二功耗组件，提供给第二功耗组件的功率被减小。 基于确定在第一或第二功耗组件中的任何一个中不能降低功率，在计算节点中强制降低功率。

公开(公告)号：US20150177796A1

公开(公告)日：2015-06-25

申请号：US14134428

申请日：2013-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Victor Zyuban

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3296 ,  Y02D10/172

Abstract: According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals. The system also includes a rotating voltage control coupled to the gate terminals and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on. A switch activation ratio level is programmable to set a number of power switch transistors in the on-state relative to a total number of power switch transistors.

Abstract translation: 根据一个实施例，提供了一种系统，其包括至少一个电力选通部件和两个或更多个功率开关晶体管，其被配置为在公共供电轨道，至少一个电力门控部件和地面之间提供一个或多个导电路径 。 两个或更多个功率开关晶体管每个包括源极端子，漏极端子和被配置为控制源极和漏极端子之间的电流的栅极端子。 该系统还包括耦合到栅极端子的旋转电压控制，并且被配置为在至少一个电力门控部件被接通的同时，将在导通状态和截止状态之间旋转的一系列控制信号施加到每个栅极端子 。 开关激活比电平是可编程的，以将多个功率开关晶体管相对于功率开关晶体管的总数设置为导通状态。

公开(公告)号：US08972782B2

公开(公告)日：2015-03-03

申请号：US13673221

申请日：2012-11-09

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Daniel A. Prener

IPC: G06F11/14

CPC classification number: G06F11/14 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F11/1405 ,  G06F12/10 ,  Y02D10/13

Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

Abstract translation: 一个方面包括在暴露流水线处理元件中提供回滚支持。 用于在暴露流水线处理元件中提供回滚支持的方法包括通过回滚支持逻辑来检测与暴露流水线处理元件中的指令的执行相关联的错误。 回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。 基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。

公开(公告)号：US20140281605A1

公开(公告)日：2014-09-18

申请号：US13837655

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3278 ,  G06F3/0656 ,  G06F9/3877 ,  G06F9/44 ,  G06F9/4893 ,  G06F13/00 ,  G06F13/1663 ,  G06F2212/312 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

Abstract translation: 实施例包括一种用于管理计算机系统中的电力的方法，所述计算机系统包括主处理器和包括供电单元的主动存储器设备，所述主存储器设备通过存储器链路与主处理器通信，所述动力单元包括处理元件。 该方法包括主处理器在程序线程上执行程序，遇到要由有源存储器件执行的代码的第一部分，通过第一命令改变有源存储器件上的供电单元的功率状态，基于 主处理器遇到第一部分代码，第一个命令包括一个存储命令。 该方法还包括处理元件在第二时间执行代码的第一部分，基于执行第一部分的处理元件，将主处理器的功率状态从功率使用状态改变到省电状态。

公开(公告)号：US20140173224A1

公开(公告)日：2014-06-19

申请号：US13714724

申请日：2012-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/3877 ,  G06F11/00 ,  G06F13/00 ,  G06F15/785

Abstract: Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values.

Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器设备中的顺序位置访问。 一个方面包括用于顺序位置访问的方法，其包括从存储器接收与处理元件上的队列条目相关联的第一组数据值。 读取与队列条目相关联并且指定提取数据值的第一子集的位置的标签值。 队列条目用从标签值指定的位置开始的数据值的第一个子集填充。 处理元件确定第一组数据值中的数据值的第二子集是否与后续的队列条目相关联，并且用数据值的第二子集填充后续队列条目的一部分。

公开(公告)号：US20140136857A1

公开(公告)日：2014-05-15

申请号：US13674224

申请日：2012-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hans M. Jacobson ,  Ravi Nair ,  John K.P. O'Brien ,  Zehra N. Sura

IPC: G06F1/26

CPC classification number: G06F9/5094 ,  G06F1/329 ,  G06F8/41 ,  G06F9/46 ,  G06F9/4893 ,  Y02D10/24

Abstract: A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement.

Abstract translation: 异构处理系统包括用于在异构处理系统中执行功率约束代码生成和调度工作的编译器。 编译器生成可由计算机执行的源代码。 编译器执行一个方法。 该方法包括将异构处理系统的功率预算分成离散数量的功率令牌。 每个功率令牌具有相等的功率单位。 该方法还包括确定在异构处理系统的处理元件上执行代码段的功率需求。 该确定基于处理元件和代码段的特性。 该方法还包括在运行时向处理元件分配至少一个功率令牌以满足功率需求。

公开(公告)号：US20140129799A1

公开(公告)日：2014-05-08

申请号：US13671679

申请日：2012-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/10

CPC classification number: G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  Y02D10/13

Abstract: Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address.

Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器件中的地址生成。 一方面包括在活动存储设备中产生地址的方法。 该方法包括从处理元件的寄存器文件组读取基地址值和偏移地址值。 处理元件根据基地址值和偏移地址值确定虚拟地址。 处理元件将虚拟地址转换为物理地址，并基于物理地址访问存储器中的位置。