Invention Grant
- Patent Title: MRAM integration techniques for technology scaling
- Patent Title (中): MRAM集成技术用于技术缩放
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Application No.: US14109200Application Date: 2013-12-17
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Publication No.: US09406875B2Publication Date: 2016-08-02
- Inventor: Xia Li , Yu Lu , Seung Hyuk Kang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L29/82
- IPC: H01L29/82 ; H01L43/12 ; H01L27/22 ; G11C11/16 ; H01L43/08
Abstract:
A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.
Public/Granted literature
- US20150171314A1 MRAM INTEGRATION TECHNIQUES FOR TECHNOLOGY Public/Granted day:2015-06-18
Information query
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