Invention Grant
- Patent Title: Stacked die integrated circuit
- Patent Title (中): 堆叠模具集成电路
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Application No.: US14220912Application Date: 2014-03-20
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Publication No.: US09418924B2Publication Date: 2016-08-16
- Inventor: Charles G. Woychik , Cyprian Emeka Uzoh , Ron Zhang , Daniel Buckminster , Guilian Gao
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L23/498 ; H01L21/52 ; H01L21/78 ; H01L23/48 ; H01L23/00 ; H01L25/065 ; H01L21/768 ; H01L21/304 ; H01L23/13
Abstract:
An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.
Public/Granted literature
- US20150270209A1 STACKED DIE INTEGRATED CIRCUIT Public/Granted day:2015-09-24
Information query
IPC分类:
