Invention Grant
- Patent Title: Cointegration of bulk and SOI semiconductor devices
- Patent Title (中): 散装和SOI半导体器件的协整
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Application No.: US14592069Application Date: 2015-01-08
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Publication No.: US09443871B2Publication Date: 2016-09-13
- Inventor: Peter Baars , Hans-Peter Moll , Jan Hoentschel
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L27/12 ; H01L21/84 ; H01L21/762 ; H01L21/321 ; H01L29/66 ; H01L21/308 ; H01L29/08 ; H01L29/417 ; H01L49/02 ; H01L27/06

Abstract:
A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.
Public/Granted literature
- US20160204128A1 COINTEGRATION OF BULK AND SOI SEMICONDUCTOR DEVICES Public/Granted day:2016-07-14
Information query
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