公开(公告)号：US20160247891A1

公开(公告)日：2016-08-25

申请号：US14628947

申请日：2015-02-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Peter Baars ,  Thorsten Kammler

IPC分类号： H01L29/49 ,  H01L23/535 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L23/535 ,  H01L21/823842 ,  H01L23/485 ,  H01L27/092 ,  H01L29/4966

摘要： A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

摘要翻译： 半导体结构包括衬底，设置在衬底上的至少一个导电柱和设置在衬底上的导电结构。 导电柱包括内部和外层，其设置在内部的下方并且在内部的侧面。 导电结构还包括内部部分和外层，其设置在内部部分的下方并且在内部部分的外侧。 导电结构环形地包围至少一个导电柱中的每一个。 所述至少一个导电柱中的每一个的外层与导电结构的外层接触。 至少一个导电柱的外层和导电结构的外层由不同的金属材料形成。

公开(公告)号：US09391156B2

公开(公告)日：2016-07-12

申请号：US14471546

申请日：2014-08-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC分类号： H01L49/02 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06 ,  H01L23/522

CPC分类号： H01L29/4983 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28132 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

摘要翻译： 提供一种制造半导体器件的方法，包括在半导体衬底上形成虚设晶体管器件的栅电极，在栅极上形成高k材料层并在栅极上形成高k材料层，并在高k材料上形成金属层 层叠并与栅电极相邻以形成电容器。

公开(公告)号：US20160064471A1

公开(公告)日：2016-03-03

申请号：US14471546

申请日：2014-08-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC分类号： H01L49/02 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06

CPC分类号： H01L29/4983 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28132 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

摘要翻译： 提供一种制造半导体器件的方法，包括在半导体衬底上形成虚设晶体管器件的栅电极，在栅极上形成高k材料层并在栅极上形成高k材料层，并在高k材料上形成金属层 层叠并与栅电极相邻以形成电容器。

公开(公告)号：US20150064872A1

公开(公告)日：2015-03-05

申请号：US14011413

申请日：2013-08-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Marco Lepper ,  Werner Graf

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/288

CPC分类号： H01L21/76804 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76877

摘要： When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

摘要翻译： 当形成先进的半导体器件的金属化层时，通常必须用金属（例如铜）填充具有高纵横比的孔。 本公开提供了一种用于在绝缘层中形成具有高纵横比的孔的方便的方法。 该绝缘层可能已经沉积在半导体器件的表面上。 所提出的方法依赖于在绝缘层上执行的离子注入步骤，随后进行蚀刻，其优选为湿蚀刻。

公开(公告)号：US08889022B2

公开(公告)日：2014-11-18

申请号：US13781874

申请日：2013-03-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Joachim Patzer

IPC分类号： B44C1/22 ,  H01L21/02

CPC分类号： H01L21/02107 ,  H01L21/32105 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32155 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66659

摘要： One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.

摘要翻译： 本文公开的一种示例性方法包括在半导体衬底上形成结构，执行保形沉积工艺以在结构上方形成未掺杂的间隔物材料层，执行成角度的离子注入工艺以在未掺杂的层中形成掺杂间隔物材料的区域 间隔材料，同时留下未掺杂的未掺杂的间隔物材料层的其它部分，并且在执行成角度离子注入工艺之后，执行至少一个蚀刻工艺，其去除未掺杂间隔物材料层的未掺杂部分，从而导致侧壁间隔物 包括位于该结构的至少一侧但不是全部侧面的掺杂间隔物材料。

公开(公告)号：US10048311B2

公开(公告)日：2018-08-14

申请号：US14848804

申请日：2015-09-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Uwe Dersch ,  Ricardo Pablo Mikalo

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  G01R31/28

摘要： A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

公开(公告)号：US09608003B2

公开(公告)日：2017-03-28

申请号：US15193770

申请日：2016-06-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC分类号： H01L29/49 ,  H01L27/12 ,  H01L21/308 ,  H01L21/321 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

摘要： An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

公开(公告)号：US09553030B2

公开(公告)日：2017-01-24

申请号：US14695232

申请日：2015-04-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Peter Baars

IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/786

CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L21/845 ,  H01L27/127 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78684

摘要： A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.

摘要翻译： 提供一种形成半导体器件的方法，包括：提供绝缘体上半导体（SOI）晶片，其包括第一半导体层，其包含第一材料成分并形成在掩埋氧化物（BOX）层上，并形成P 通道晶体管器件，包括只在第一半导体层的第一部分上形成第二半导体层，其中第二半导体层包括第一材料成分和与第一材料成分不同的第二材料成分，在第一 半导体层，然后进行热退火，以将第二材料成分从第二半导体层推入第一半导体层。

公开(公告)号：US20160343659A1

公开(公告)日：2016-11-24

申请号：US14718502

申请日：2015-05-21

申请人： GLOBALFOUNDRIES Inc.

发明人： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC分类号： H01L23/525 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L23/5256 ,  H01L21/84 ,  H01L27/1203

摘要： A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

摘要翻译： 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09466685B2

公开(公告)日：2016-10-11

申请号：US14628947

申请日：2015-02-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Hans-Peter Moll ,  Peter Baars ,  Thorsten Kammler

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238

CPC分类号： H01L23/535 ,  H01L21/823842 ,  H01L23/485 ,  H01L27/092 ,  H01L29/4966

摘要： A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

摘要翻译： 半导体结构包括衬底，设置在衬底上的至少一个导电柱和设置在衬底上的导电结构。 导电柱包括内部和外层，其设置在内部的下方并且在内部的侧面。 导电结构还包括内部部分和外层，其设置在内部部分的下方并且在内部部分的外侧。 导电结构环形地包围至少一个导电柱中的每一个。 所述至少一个导电柱中的每一个的外层与导电结构的外层接触。 至少一个导电柱的外层和导电结构的外层由不同的金属材料形成。