Invention Grant
- Patent Title: Semiconductor interconnect structures
- Patent Title (中): 半导体互连结构
-
Application No.: US14746315Application Date: 2015-06-22
-
Publication No.: US09455224B2Publication Date: 2016-09-27
- Inventor: Boyan Boyanov , Kanwal Jit Singh , James Clarke , Alan Myers
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L23/528 ; H01L23/522 ; H01L21/768 ; H01L23/532

Abstract:
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
Public/Granted literature
- US20150294935A1 SEMICONDUCTOR INTERCONNECT STRUCTURES Public/Granted day:2015-10-15
Information query
IPC分类: