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    SEMICONDUCTOR INTERCONNECT STRUCTURES
    1.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURES 有权

    公开(公告)号：US20170011998A1

    公开(公告)日：2017-01-12

    申请号：US15276385

    申请日：2016-09-26

    Applicant: INTEL CORPORATION

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

    IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

    Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

    Semiconductor interconnect structures
    2.
    发明授权
    Semiconductor interconnect structures 有权
    半导体互连结构

    公开(公告)号：US09455224B2

    公开(公告)日：2016-09-27

    申请号：US14746315

    申请日：2015-06-22

    Applicant: INTEL CORPORATION

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

    IPC: H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

    Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

    SEMICONDUCTOR INTERCONNECT STRUCTURES
    3.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURES 审中-公开

    公开(公告)号：US20150294935A1

    公开(公告)日：2015-10-15

    申请号：US14746315

    申请日：2015-06-22

    Applicant: INTEL CORPORATION

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

    IPC: H01L23/528 ,  H01L23/522

    CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

    Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

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