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    METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS
    3.
    发明申请
    METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS 有权

    公开(公告)号：US20220270978A1

    公开(公告)日：2022-08-25

    申请号：US17742792

    申请日：2022-05-12

    Applicant: Intel Corporation

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

    Methods and apparatuses to form self-aligned caps
    4.
    发明授权
    Methods and apparatuses to form self-aligned caps 有权

    公开(公告)号：US10727183B2

    公开(公告)日：2020-07-28

    申请号：US16559086

    申请日：2019-09-03

    Applicant: Intel Corporation

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

    Methods and apparatuses to form self-aligned caps
    5.
    发明授权
    Methods and apparatuses to form self-aligned caps 有权

    公开(公告)号：US10446493B2

    公开(公告)日：2019-10-15

    申请号：US15477506

    申请日：2017-04-03

    Applicant: INTEL CORPORATION

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

    SEMICONDUCTOR INTERCONNECT STRUCTURES
    7.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURES 有权

    公开(公告)号：US20170011998A1

    公开(公告)日：2017-01-12

    申请号：US15276385

    申请日：2016-09-26

    Applicant: INTEL CORPORATION

    Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

    IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

    Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

    Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
    10.
    发明授权
    Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects 有权
    自对准通孔和插头图案化，用于后端（BEOL）互连的光触点

    公开(公告)号：US09553018B2

    公开(公告)日：2017-01-24

    申请号：US14965734

    申请日：2015-12-10

    Applicant: Intel Corporation

    Inventor： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

    IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/027 ,  H01L23/532

    CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

    Abstract translation: 描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。 在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中 第二光栅的线。 介电材料的区域由交联的可光致发光材料组成。

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