Invention Grant
US09461058B2 Methods of fabricating semiconductor devices including multiple patterning
有权
制造包括多个图案化的半导体器件的方法
- Patent Title: Methods of fabricating semiconductor devices including multiple patterning
- Patent Title (中): 制造包括多个图案化的半导体器件的方法
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Application No.: US15016737Application Date: 2016-02-05
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Publication No.: US09461058B2Publication Date: 2016-10-04
- Inventor: Min-Sung Song , Jae-Hwang Sim , Joon-Sung Lim
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel & Sibley, P.A.
- Priority: KR10-2015-0019497 20150209
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/115 ; H01L29/66 ; H01L21/311 ; H01L21/308 ; H01L21/02 ; H01L29/06 ; H01L29/788

Abstract:
Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.
Public/Granted literature
- US20160233223A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING MULTIPLE PATTERNING Public/Granted day:2016-08-11
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