公开(公告)号：USRE50137E1

公开(公告)日：2024-09-17

申请号：US17586023

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Zhiliang Xia ,  Ahn-Sik Moon ,  Se-Jun Park ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US12022653B2

公开(公告)日：2024-06-25

申请号：US17162526

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20240014157A1

公开(公告)日：2024-01-11

申请号：US18349017

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B41/27 ,  H10B43/27 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US20230180476A1

公开(公告)日：2023-06-08

申请号：US18054730

申请日：2022-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Jisu Shin ,  Byungik Yoo ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device and an electronic system including the same are discussed. The device may include: a stack structure including electrode layers and inter-electrode insulating layers that are alternately stacked on a substrate; one or more vertical semiconductor structures that extend into the stack structure and are adjacent to the substrate; one or more vertical conductive structures arranged in a first direction between adjacent ones of the one or more vertical semiconductor structures and extending into the stack structure and are adjacent to the substrate; and a conductive line portion on the stack structure that extends in the first direction to connect the one or more vertical conductive structures to each other. The conductive line portion and the vertical conductive structures may be connected to form a single unit.

公开(公告)号：US11296102B2

公开(公告)日：2022-04-05

申请号：US16858983

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Woosung Yang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  G11C5/06 ,  G11C5/02

Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

公开(公告)号：US11289504B2

公开(公告)日：2022-03-29

申请号：US16777776

申请日：2020-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Dong-Sik Lee ,  Sung-Min Hwang ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/28 ,  H01L29/66

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US20190043881A1

公开(公告)日：2019-02-07

申请号：US15982216

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungjoong Kim ,  Joon-Sung Lim ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/423 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/6681

Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

公开(公告)号：US20180358372A1

公开(公告)日：2018-12-13

申请号：US15989477

申请日：2018-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung Lim ,  Gilsung Lee ,  Eunsuk Cho

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/24

CPC classification number: H01L27/11573 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.

公开(公告)号：US12213315B2

公开(公告)日：2025-01-28

申请号：US17687131

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjin Lee ,  Dong-Sik Lee ,  Joon-Sung Lim

IPC: H10B43/27 ,  H10B43/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/51

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

公开(公告)号：US11792982B2

公开(公告)日：2023-10-17

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Hojun Seong ,  Joonhee Lee ,  Joon-Sung Lim ,  Euntaek Jung

IPC: H01L27/11582 ,  H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.