Invention Grant
- Patent Title: Techniques for putting platform subsystems into a lower power state in parallel
- Patent Title (中): 将平台子系统并入较低功率状态的技术
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Application No.: US14040156Application Date: 2013-09-27
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Publication No.: US09471132B2Publication Date: 2016-10-18
- Inventor: Vasudev Bibikar , Rajith K. Mavila
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/32

Abstract:
Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.
Public/Granted literature
- US20150095677A1 TECHNIQUES FOR PUTTING PLATFORM SUBSYSTEMS INTO A LOWER POWER STATE IN PARALLEL Public/Granted day:2015-04-02
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