公开(公告)号：US09471132B2

公开(公告)日：2016-10-18

申请号：US14040156

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Vasudev Bibikar ,  Rajith K. Mavila

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.

Abstract translation: 各种实施例通常涉及用于确定具有用于进入较低功率状态的相关联的子系统睡眠控制寄存器的多个子系统中的每一个的睡眠配置状态的装置，方法和其他技术，配置每个相关联的子系统睡眠控制寄存器 具有每个子系统的睡眠配置状态，并且当转换到较低功率状态时并行地启用每个子系统的睡眠配置状态。