Invention Grant
US09472596B2 Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof
有权
用于改善RRAM可靠性的金属线路连接，包括其的半导体布置及其制造
- Patent Title: Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof
- Patent Title (中): 用于改善RRAM可靠性的金属线路连接，包括其的半导体布置及其制造
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Application No.: US14967697Application Date: 2015-12-14
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Publication No.: US09472596B2Publication Date: 2016-10-18
- Inventor: Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweilier & Associates, LLC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; H01L27/24 ; G11C13/00 ; H01L23/528 ; H01L45/00
Abstract:
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.
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