Invention Grant
- Patent Title: Write combining cache microarchitecture for synchronization events
- Patent Title (中): 为同步事件写入组合缓存微架构
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Application No.: US13961561Application Date: 2013-08-07
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Publication No.: US09477599B2Publication Date: 2016-10-25
- Inventor: Blake A. Hechtman , Bradford M. Beckmann
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F12/08 ; G06F12/12

Abstract:
A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read/write combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events since a store event may not need to reach main memory to complete.
Public/Granted literature
- US20150046652A1 WRITE COMBINING CACHE MICROARCHITECTURE FOR SYNCHRONIZATION EVENTS Public/Granted day:2015-02-12
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