Invention Grant
- Patent Title: Apparatus and methods for frequency lock enhancement of phase-locked loops
- Patent Title (中): 锁相环频率锁定增强的装置和方法
-
Application No.: US14134767Application Date: 2013-12-19
-
Publication No.: US09484935B2Publication Date: 2016-11-01
- Inventor: Hyman Shanan , Michael F. Keaveney
- Applicant: ANALOG DEVICES GLOBAL
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Global
- Current Assignee: Analog Devices Global
- Current Assignee Address: BM Hamilton
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/099 ; H03L1/02 ; H03L7/10

Abstract:
Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.
Public/Granted literature
- US20150180485A1 APPARATUS AND METHODS FOR FREQUENCY LOCK ENHANCEMENT OF PHASE-LOCKED LOOPS Public/Granted day:2015-06-25
Information query